On the First Separating Redundancy of Array LDPC Codes

Decoding of Array Ldpc Codes Using On-the –fly Computation

Message passing memory takes around 30% of chip area and consumes from 50%-90% power of the typical semiparallel decoders for the Low Density Parity Check Codes (LDPC). We propose a new LDPC Decoder architecture based on the Min Sum algorithm that reduces the need of message passing memory by 80% and the routing requirements by more than 50%. This novel architecture is based on scheduling of co...

Bounds on separating redundancy

It is known that any linear code allows for a decoding strategy that treats errors and erasures separately over an error-erasure channel. In particular, a carefully designed paritycheck matrix makes efficient erasure correction possible through iterative decoding while instantly providing the necessary paritycheck equations for independent error correction on demand. The separating redundancy o...

on the girth of tanner (3,7) quasi-cyclic ldpc codes

‎s‎. ‎kim et al‎. ‎have been analyzed the girth of some algebraically‎ ‎structured quasi-cyclic (qc) low-density parity-check (ldpc)‎ ‎codes‎, ‎i.e‎. ‎tanner $(3,5)$ of length $5p$‎, ‎where $p$ is a prime of‎ ‎the form $15m+1$‎. ‎in this paper‎, ‎by extension this method to‎ ‎tanner $(3,7)$ codes of length $7p$‎, ‎where $p$ is a prime of the‎ ‎form $21m‎+ ‎1$‎, ‎the girth values of tanner $(3,7...

Incremental Redundancy Hybrid-ARQ with Rate Compatible LDPC Codes

Hybrid ARQ (HARQ) is well known link adaptation scheme which improves system throughput combining the error correcting codes and retransmission scheme. The incremental redundancy (IR) HARQ transmits parity bits incrementally when the retransmission is requested and normally provides higher throughput than the Chase combining by adaptive transmission in accordance with channel variations. In thi...

On the Grobner Basis of a Family of Quasi-Cyclic LDPC Codes